The manufacturing of integrated circuits comprises numerous discrete processing steps. The steps begin with a slice of crystal silicon or some other semiconductor material, referred to as a “wafer”. The steps of the manufacturing process, such as masking and etching, chemical depositions, etc., are then performed in a specific order on the wafer to fabricate the integrated circuits.
Typically, wafers move through the manufacturing flow in batches, referred to as “lots”. The wafers are first placed within a cassette prior to a first process tool or apparatus. The first process tool performs the first step or set of steps of the manufacturing process. The first process tool removes the wafers from the cassette one at a time for processing. As the first process tool finishes with a wafer, it is placed into another cassette or into the same cassette, and then moved to a second process tool. The second process tool also removes the wafers from the cassette one at a time for processing. As the second process tool finishes with a wafer, it is placed into another cassette or into the same cassette and moved to the next process tool. This continues until each step of the manufacturing process is completed. A typical manufacturing process involves several hundred steps, each step performed by a different process tool.
At the completion of the wafer processing, the wafers are tested to determine circuit functionality. The wafer is then sliced, and the functioning integrated circuits on the wafer are packaged. The number of functioning integrated circuits on a wafer relative to the total number of integrated circuits fabricated is referred to as the “yield” of the wafer. However, the yields of the wafers within the same lot may vary. One reason for this within-lot yield variation is the order at which the wafers in the lot are processed at one or more processing steps due to non-optimal condition of the tools at those steps. To determine which processing step(s) could have attributed to the yield variation, the processing sequences of the wafers at various steps are tracked. These orders are then correlated with the wafer-level yield. Randomizing the order of the wafers prior to some of these steps is often done to ensure traceability of significant signals.
In prior analysis practice, the processing sequences and the yields are fed into a factory control system. Then, the graphs of the yields versus the processing sequences are generated. The graphs are analyzed to discern trends in the graphs. However, most processes comprise many steps. Wafer handlers are needed to perform the randomization. Although the randomization of the wafer order before each processing step effectively isolates the step responsible for any significant trend, such practice is cost prohibitive. In a large fabrication where there are many hundreds of process steps, a large number of wafer handlers would be needed for randomization, making the financial costs extremely high. To reduce costs, randomization is performed at intervals of steps, such as at every ten or twenty steps, rather than at each step. Further analysis to isolate the responsible step is then required, reducing the efficiency of the analysis.
Accordingly, there exists a need for an improved method for detecting sequential processing effects on integrated circuits to be manufactured in a manufacturing process. The improved method should allow for randomization at each process tool of the manufacturing process without significantly increasing the costs of manufacturing the integrated circuits. The present invention addresses such a need.